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LTC6991
11
6991fb
OPERATION
RST Pin and Polarity (POL) Bit
The RST pin controls the state of the LTC6991’s output
as seen on the OUT pin. The active/inactive voltage levels
depend on the POL bit setting.
Table 2. Output States
POL BIT
RST PIN
OUTPUT STATE
0
Oscillating
0
1
0 (reset)
1
0
1 (reset)
1
Oscillating
Each period of the LTC6991’s internal oscillator clocks the
output state latch (see Block Diagram). The reset pin (RST)
can reset or hold off the output latch. The active state of
the reset pin is determined by the polarity function (POL).
Similarly, the output latch is followed by a buffer that can
invert the output. The output polarity is also controlled
by the POL bit.
If POL = 0, the reset pin is active high and the output latch
is not inverted. Therefore, pulling the RST pin high will
reset the output latch and force the OUT pin low. Pulling
RST low will allow the output to oscillate, with the next
rising edge dependent on the internal oscillator.
If POL = 1, the reset pin is active low and the output latch
is inverted. Therefore, pulling the RST pin low will reset
the output latch and force the OUT pin high. Pulling RST
high will allow the output to oscillate, with the next falling
edge dependent on the internal oscillator.
Note that the master oscillator frequency and phase are not
affected by the RST pin; The LTC6991 continues to oscil-
late, internally, even when RST is active. While the reset
function can block an output pulse, its exact placement in
time can only be changed by power cycling the LTC6991.
tOUT
RST
OUT
tRST
tWIDTH
INTERNAL
OSCILLATOR
6991 F03
tOUT
RST
OUT
tRST
INTERNAL
OSCILLATOR
6991 F04
Figure 3. RST Timing Diagram (POL = 0)
Figure 4. RST Timing Diagram (POL = 1)
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